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?2003 silicon storage technology, inc. s71244-01-000 11/03 1 the sst logo, superflash, and flashbank are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. preliminary specifications 16 mbit (x16/x8) concurrent superflash memory SST34HF1601B features: ? organized as 1m x16 or 2m x8 dual bank architecture for concurrent read/write operation ? bank1: 12 mbit (768k x16/1536k x8) flash ? bank2: 4 mbit (256k x16/512k x8) flash single 2.7-3.3v for read and write operations superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention low power consumption: ? active current: 6 ma typical ? standby current: 4 a typical hardware sector protection/wp# input pin ? protects 4 outermost blocks in the smaller bank (128 kword/256 kbyte) hardware reset pin (rst#) sector-erase capability ? uniform 1 kword/2 kbyte sectors block-erase capability ? uniform 32 kword/64 kbyte blocks fast read access time ? 80 ns latched address and data fast erase and word-program (typical): ? sector-erase time: 18 ms ? block-erase time: 18 ms ? chip-erase time: 70 ms ? word-program time: 14 s ? byte-program time: 14 s ? chip rewrite time: 8 seconds (word mode) ? chip rewrite time: 16 seconds (byte mode) automatic write timing ? internal v pp generation end-of-write detection ? toggle bit ? data# polling ? ready/busy# pin cmos i/o compatibility jedec standards ? flash eeprom pinouts and command sets packages available ? 48-lead tsop (12mm x 20mm) ? 56-ball tfbga (8mm x 10mm) product description the SST34HF1601B consists of two memory banks, bank1 is 256k x16 or 512k x8 and bank2 is 768k x16 or 1536k x8 which are cmos concurrent read/write flash memories manufactured with sst?s proprietary, high-per- formance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the SST34HF1601B writes (program or erase) with a 2.7-3.3v power supply. the SST34HF1601B device conforms to jedec standard pin assignments for x16/x8 memories. featuring high-performance word-program, the SST34HF1601B device provides a typical word-program time of 14 sec. the devices use toggle bit or data# poll- ing to detect the completion of the program or erase opera- tion. to protect against inadvertent writes, the SST34HF1601B device has on-chip hardware and soft- ware data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, the SST34HF1601B device is offered with a guaranteed endurance of 10,000 cycles. data retention is rated at greater than 100 years. the SST34HF1601B is suited for applications that require convenient and economical updating of program, configu- ration, or data memory. for all system applications, the SST34HF1601B significantly improves performance and reliability, while lowering power consumption. the SST34HF1601B inherently uses less energy during erase and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, cur- rent, and time of application. since for any given voltage range, the superflash technology uses less current to pro- gram and has a shorter erase time, the total energy con- sumed during any erase or program operation is less than alternative flash technologies. the SST34HF1601B also improves flexibility while lowering the cost for program, data, and configuration storage applications. SST34HF1601B16mb (x16/x8) dual-bank csf memory
2 preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B ?2003 silicon storage technology, inc. s71244-01-000 11/03 the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. to meet high density, surface mount requirements, the SST34HF1601B is offered in 48-lead tsop and 56-ball bga packages. see figures 2 and 3 for pin assignments. device operation all memory banks share common i/o lines, we# and oe#. memory bank selection is by bank select address (a 19 , a 18 ). we# is used with sdp to control the erase and pro- gram operations in each memory bank. commands are used to initiate the memory operation func- tions of the device. commands are written to the device using standard microprocessor write sequences. a com- mand is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. concurrent read/write operation dual bank architecture of SST34HF1601B device allows the concurrent read/write operation whereby the user can read from one bank while programming or erasing in the other bank. this operation can be used when the user needs to read system code in one bank while updating data in the other bank. note: for the purposes of this table, write means to perform block-, sector-, or chip-erase or word-program operations as appli- cable to the appropriate bank. read operation the read operation of the SST34HF1601B is con- trolled by ce# and oe#; both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data on the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 4). word-program operation the SST34HF1601B is programmed on a word-by-word basis. before programming, the sector where the word exists must be fully erased. the program operation con- sists of three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word- program operation, the addresses are latched on the fall- ing edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal pro- gram operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the pro- gram operation, once initiated, will be completed typically within 10 s. see figures 5 and 6 for we# and ce# con- trolled program operation timing diagrams and figure 18 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. after detecting the completion of a word-/byte-program operation (either through ry/ by# line, data# polling, or toggle bit), the host must keep ce# signal low for a minimum duration of bus recovery time (t br = ~1 s) before valid data can be read correctly. please see figures 5 through 8 for cor- responding ac timing diagrams. c oncurrent r ead /w rite s tate bank 1 bank 2 read no operation read write write read write no operation no operation read no operation write
preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B 3 ?2003 silicon storage technology, inc. s71244-01-000 11/03 sector- (block-) erase operation the sector- (block-) erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. the SST34HF1601B offers both sector-erase and block-erase mode. the sector architecture is based on uniform sector size of 1 kword/2 kbyte. the block-erase mode is based on uniform block size of 32 kword/64 kbyte. the sector-erase operation is initiated by executing a six-byte command sequence with sector-erase com- mand (30h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six- byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. see figures 10 and 11 for timing waveforms. any com- mands issued during the sector- or block-erase operation are ignored. chip-erase operation the SST34HF1601B provides a chip-erase operation, which allows the user to erase all unprotected sectors/ blocks to the ?1? state. this is useful when the device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 9 for timing dia- gram, and figure 21 for the flowchart. any commands issued during the chip-erase operation are ignored. write operation status detection the SST34HF1601B provides one hardware and two soft- ware means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the hardware detection uses the ready/busy# (ry/ by#) output pin. the software detection includes two sta- tus bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a ready/busy# (ry/ by#), a data# polling (dq 7 ) or toggle bit (dq 6 ) read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an errone- ous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has com- pleted the write cycle, otherwise the rejection is valid. ready/busy# (ry/by#) the SST34HF1601B includes a ready/busy# (ry/by#) output signal. ry/by# is actively pulled low while during an internal erase or program operation is in progress. ry/by# is an open drain output that allows several devices to be tied in parallel to v dd via an external pull up resistor. ry/ by# is high impedance whenever ce# is high or rst# is low. there is a 1 s bus recovery time (t br ) required before valid data can be read on the data bus. new commands can be entered immediately after ry/by# goes high. byte/word (ciof) this device includes a ciof pin to control whether the data i/o pins operate as either x8 or x16. if the ciof pin is at logic ?1? (v ih ) the device is in x16 data configuration; all data i/o pins dq 15 -dq 0 are active and controlled by ce# and oe#. if the ciof pin is at logic ?0?, the device is in x8 data config- uration; only data i/o pins dq 7 -dq 0 are active and con- trolled by ce# and oe#. the remaining data pins dq 14 - dq 8 are at high z and pin dq 15 is used as the address input (a -1 ) for the least significant bit of the address bus. data# polling (dq 7 ) when the SST34HF1601B is in the internal program oper- ation, any attempt to read dq 7 will produce the comple- ment of the true data. once the program operation is completed, dq 7 will produce true data. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block-, or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 7 for data# polling (dq 7 ) timing diagram and figure 19 for a flowchart. there is a 1 s bus recovery time (t br ) required before valid data can be read on the data bus. new commands can be entered immediately after dq 7 becomes true data.
4 preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B ?2003 silicon storage technology, inc. s71244-01-000 11/03 toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sec- tor-, block- or chip-erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 8 for toggle bit timing diagram and figure 19 for a flowchart. there is a 1 s bus recovery time (t br ) required before valid data can be read on the data bus. new commands can be entered immediately after dq 6 no longer toggles. data protection the SST34HF1601B provides both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this prevents inadvert- ent writes during power-up or power-down. hardware bloc k protection the SST34HF1601B provides a hardware block protection which protects the top 4 blocks of bank 2, 128 kword/256 kbyte in the smaller bank. the block is protected when wp# is held low. see figure 1 for block-protection location. a user can disable block protection by driving wp# high thus allowing erase or program of data into the protected sectors. wp# must be held high prior to issuing the write command and remain stable until after the entire write operation has completed. hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when the rst# pin is held low for at least t rp, any in-progress operation will terminate and return to read mode (see figure 15). when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place (see figure 14). the erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. software data protection (sdp) the SST34HF1601B provides the jedec standard soft- ware data protection scheme for all data alteration opera- tions, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. the SST34HF1601B is shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid commands will abort the device to read mode within t rc. the contents of dq 15 - dq 8 can be v il or v ih , but no other value during any sdp command sequence.
preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B 5 ?2003 silicon storage technology, inc. s71244-01-000 11/03 product identification the product identification mode identifies the device and manufacturer. for details, see table 4 for software opera- tion, figure 12 for the software id entry and read timing diagram and figure 20 for the software id entry command sequence flowchart. product identification mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that appar- ently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit com- mand is ignored during an internal program or erase oper- ation. see table 4 for the software command code, figure 13 for timing waveform and figure 20 for a flowchart. table 1: p roduct i dentification word data manufacturer?s id 0000h 00bfh device id SST34HF1601B 0001h 2762h t1.0 1244 1244 b01.1 superflash memory 12 mbit bank (x16/x8) i/o buffers superflash memory 4 mbit bank (x16/x8) memory address dq 15 - dq 0 (a -1 ) ce# wp# we# oe# control logic rst# ciof ry/by# address buffers (4 kword sector protection) f unctional b lock d iagram
6 preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 1: SST34HF1601B, 1 m bit x 16 c oncurrent s uper f lash d ual -b ank m emory o rganization fffffh f8000h block 31 f7fffh f0000h block 30 effffh e8000h block 29 e7fffh e0000h block 28 dffffh d8000h block 27 d7fffh d0000h block 26 cffffh c8000h block 25 c7fffh c0000h block 24 bank 2 bffffh b8000h block 23 b7fffh b0000h block 22 affffh a8000h block 21 a7fffh a0000h block 20 9ffffh 98000h block 19 97fffh 90000h block 18 8ffffh 88000h block 17 87fffh 80000h block 16 7ffffh 78000h block 15 77fffh 70000h block 14 6ffffh 68000h block 13 67fffh 60000h block 12 5ffffh 58000h block 11 57fffh 50000h block 10 4ffffh 48000h block 9 47fffh 40000h block 8 3ffffh 38000h block 7 37fffh 30000h block 6 2ffffh 28000h block 5 27fffh 20000h block 4 1ffffh 18000h block 3 17fffh 10000h block 2 00ffffh 008000h block 1 007fffh 000000h block 0 bank 1 top four blocks protection; 32 kword blocks; 1 kword sectors 1244 f01.2 128 kword block protection
preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B 7 ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 2: p in a ssignments for 48- lead tsop (12 mm x 20 mm ) figure 3: p in a ssignments for 56- ball lfbga (8 mm x 10 mm ) a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we# rst# nc wp# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 ciof v ss dq15/a -1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1244 48-tsop p1.1 standard pinout to p v i e w die up 1244 56-lfbga p2.0 a11 a8 we# wp# nc a7 a15 a12 a19 nc rst# nc a6 a3 nc a13 a9 nc ry/by# a18 a5 a2 nc a14 a10 a17 a4 a1 a16 nc dq6 dq1 v ss a0 ciof note* dq13 dq4 dq3 dq9 oe# ce# v ss dq7 dq12 nc v dd dq10 dq0 nc dq14 dq5 nc dq11 dq2 dq8 a b c d e f g h 8 7 6 5 4 3 2 1 top view (balls facing down) note: f7 = dq15/a -1
8 preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B ?2003 silicon storage technology, inc. s71244-01-000 11/03 table 2: p in d escription symbol name functions a 19 -a 0 address inputs to provide memory addresses. during sector-erase and hardware sector protection, a 19 -a 10 address lines will select the sector. during block-erase a 19 -a 15 address lines will select the block. dq 14 - dq 0 data input/output (15 pins) to output data during read cycles and receive input data during write cycles data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. dq 15 /a -1 data i/o and lsb address dq 15 is used as a data i/o pin when in x16 mode (ciof=?1?) a-1 is used as the lsb address input pin when in x8 mode (ciof=?0?) ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers we# write enable to control the write operations ciof byte selection for flash when low, select byte mode. when high, select word mode. rst# hardware reset to reset and return the device to read mode ry/by# ready/busy# to output the status of a program or erase operation ry/by# is a open drain output, so a 10k ? - 100k ? pull-up resistor is required to allow ry/by# to transition high indicating the device is ready to read. wp# write protect to protect and unprotect the bottom 4 sectors from erase or program operation. v dd power supply to provide 2.7-3.3v power supply voltage v ss ground nc no connection unconnected pins t2.0 1244 table 3: o peration m odes s election mode ce# oe# we# dq 7 -dq 0 dq 15 -dq 8 address ciof = v ih ciof = v il read v il v il v ih d out d out dq 14 -dq 8 = high z a in program v il v ih v il d in d in dq 15 = a -1 a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. x high z sector or block address, xxh for chip-erase standby v ih x x high z high z high z x write inhibit x v il xhigh z / d out high z / d out high z x xxv ih high z / d out high z / d out high z x product identification software mode v il v il v ih manufacturer?s id (bfh) manufacturer?s id (00h) high z see table 4 device id 2 2. device id = 2762h device id 2 high z t3.1 1244
preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B 9 ?2003 silicon storage technology, inc. s71244-01-000 11/03 table 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5,6 5555h aah 2aaah 55h 5555h 90h software id exit 5555h aah 2aaah 55h 5555h f0h t4.0 1244 1. address format a 14 -a 0 (hex), addresses a 19 - a 15 can be v il or v ih , but no other value, for the command sequence in x16 mode. for x8 mode, addresses a 19 - a 15, a -1 (lsb) , and dq 14 -dq 8 can be v il or v ih , but no other value, for the command sequence. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for the command sequence. 3. wa = program word address 4. sa x for sector-erase; uses a 19 -a 10 address lines ba x for block-erase; uses a 19 -a 15 address lines 5. the device does not remain in software product identification mode if powered down. 6. with a 19 -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 = 0 SST34HF1601B device id = 2762h, is read with a 0 = 1 absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) for tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 0c output short circuit current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma o perating r ange : range ambient temp v dd commercial 0c to +70c 2.7-3.3v extended -20c to +85c 2.7-3.3v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 16 and 17
10 preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B ?2003 silicon storage technology, inc. s71244-01-000 11/03 table 5: dc o perating c haracteristics v dd = 2.7-3.3v symbol parameter limits test conditions min max units i dd active v dd current address input=v ilt /v iht, at f=1/t rc min, v dd =v dd max read 35 ma ce#=oe#=v il , we#=v ih , all i/os open program and erase 40 ma ce#=v il , oe#=v ih concurrent read/write 75 ma i sb standby v dd current 30 a ce#=v ihc , v dd =v dd max i rt reset v dd current 20 a rst# = v ss 0.3v i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t5.0 1244 table 6: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t6.0 1244 table 7: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. i/o pin capacitance v i/o = 0v 10 pf c in 1 input capacitance v in = 0v 10 pf t7.0 1244 table 8: r eliability c haracteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t8.0 1244
preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B 11 ?2003 silicon storage technology, inc. s71244-01-000 11/03 ac characteristics table 9: r ead c ycle t iming p arameters v dd = 2.7-3.3v symbol parameter SST34HF1601B-80 units min max t rc read cycle time 80 ns t ce chip enable access time 80 ns t aa address access time 80 ns t oe output enable access time 40 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 30 ns t ohz 1 oe# high to high-z output 30 ns t oh 1 output hold from address change 0 ns t rp 1 rst# pulse width 500 ns t rhr 1 rst# high before read 50 ns t ry 1,2 2. this parameter applies to sector-e rase, block-erase and program operations. this parameter does not apply to chip-erase operations. rst# pin low to read mode 150 s t9.0 1244 table 10: p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp word-program time 20 s t as address setup time 0 ns t ah address hold time 40 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 100 ms t by 1 ry/by# delay time 90 ns t br bus# recovery time 1 s t10.0 1244
12 preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 4: r ead c ycle t iming d iagram for w ord mode (f or b yte mode a -1 = a ddress i nput ) figure 5: we# c ontrolled w ord -p rogram c ycle t iming d iagram for w ord mode (f or b yte mode a -1 = a ddress i nput ) 1244 f03.0 addresses dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 1244 f04.1 address a 19-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs t by ce# ry/by# 5555 2aaa 5555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# t br t bp note: x can be v il or v ih , but no other value. valid
preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B 13 ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 6: ce# c ontrolled w ord -p rogram c ycle t iming d iagram for w ord mode (f or b yte mode a -1 = a ddress i nput ) figure 7: d ata # p olling t iming d iagram for w ord mode (f or b yte mode a -1 = a ddress i nput ) valid 1244 f05.1 address a 19-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# 5555 2aaa 5555 addr xxaa xx55 xxa0 data word (addr/data) oe# ce# t bp t by ry/by# t br note: x can be v il or v ih , but no other value. 1244 f06.1 address a 19-0 dq 7 data# data# valid data we# oe# ce# t oeh t oe t ce t oes t br
14 preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 8: t oggle b it t iming d iagram for w ord mode (f or b yte mode a -1 is don ? t care ) figure 9: we# c ontrolled c hip -e rase t iming d iagram for w ord mode (f or b yte mode a -1 is don ? t care ) 1244 f07.1 address a 19-0 dq 6 we# oe# ce# t oe t oeh t ce two read cycles with same outputs valid data t br valid t br 1244 f08.1 address a 19-0 dq 15-0 we# 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# ce# six-byte code for chip-erase t sce t wp t by ry/by# note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 10) x can be v il or v ih , but no other value.
preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B 15 ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 10: we# c ontrolled b lock -e rase t iming d iagram for w ord mode (f or b yte mode a -1 is don ? t care ) figure 11: we# c ontrolled s ector -e rase t iming d iagram for w ord mode (f or b yte mode a -1 is don ? t care ) 1244 f09.1 address a 19-0 dq 15-0 we# 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# ce# six-byte code for block-erase t wp t by ry/by# valid t br t be note: this device also supports ce# controlled block-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 10) ba x = block address x can be v il or v ih , but no other value. 1244 f10.1 address a 19-0 dq 15-0 we# 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# ce# six-byte code for sector-erase t wp t by ry/by# valid t br t se note: this device also supports ce# controlled sector-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 10) sa x = sector address x can be v il or v ih , but no other value.
16 preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 12: s oftware id e ntry and r ead for w ord mode (f or b yte mode a -1 = 0) figure 13: s oftware id e xit for w ord mode (f or b yte mode a -1 = 0) 1244 f11.0 addresses t ida dq 15-0 we# device id = 2762h for SST34HF1601B 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: x can be v il or v ih , but no other value. 1244 f13.0 addresses dq 15-0 t ida t wp t wph we# 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: x can be v il or v ih , but no other value.
preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B 17 ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 14: rst# t iming ( when no internal operation is in progress ) figure 15: rst# t iming ( during s ector - or b lock -e rase operation ) 1244 f14.0 ry/by# 0v rst# ce#/oe# t rp t rhr 1244 f15.1 ry/by# ce# oe# t rp t ry t br rst#
18 preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 16: ac i nput /o utput r eference w aveforms figure 17: a t est l oad e xample 1244 f16.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1244 f17.0 to tester to dut c l
preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B 19 ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 18: w ord -p rogram a lgorithm 1244 f18.0 start load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxa0h address: 5555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value.
20 preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 19: w ait o ptions 1244 f19.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B 21 ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 20: s oftware p roduct id c ommand f lowcharts 1244 f20.1 load data: xxaah address: 5555h software product id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h software id exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h wait t ida return to normal operation note: x can be v il or v ih , but no other value.
22 preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B ?2003 silicon storage technology, inc. s71244-01-000 11/03 figure 21: e rase c ommand s equence 1244 f21.0 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait t se sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait t be block erased to ffffh note: x can be v il or v ih , but no other value.
preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B 23 ?2003 silicon storage technology, inc. s71244-01-000 11/03 product ordering information valid combinations for SST34HF1601B SST34HF1601B-80-4c-ek SST34HF1601B-80-4c-b1p SST34HF1601B-80-4e-ek SST34HF1601B-80-4e-b1p note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations. device speed suffix1 suffix2 sst34 h f160 1 b-xxx -x x -x x package modifier k = 48 leads p = 56 balls package type e = tsop (type 1, die up, 12mm x 20mm) b1 = tfbga (8mm x 10mm) temperature range c = commercial = 0c to +70c e = extended = -20c to +85c minimum endurance 4 = 10,000 cycles read access speed 80 = 80 ns bank split 1 = 12 mbit + 4 mbit device density 160 = 1mbit x16 or 2mbit x8 voltag e h = 2.7-3.3v product series 34 = concurrent superflash + sram combomemory
24 preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B ?2003 silicon storage technology, inc. s71244-01-000 11/03 packaging diagrams 48- lead t hin s mall o utline p ackage (tsop) 12 mm x 20 mm sst p ackage c ode : ek 1.05 0.95 0.70 0.50 18.50 18.30 20.20 19.80 0.70 0.50 12.20 11.80 0.27 0.17 0.15 0.05 48-tsop-ek-8 note: 1. complies with jedec publication 95 mo-142 dd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm 0?- 5? detail pin # 1 identifier 0. 50 bsc
preliminary specifications 16 mbit concurrent superflash memory SST34HF1601B 25 ?2003 silicon storage technology, inc. s71244-01-000 11/03 56- ball t hin - profile , f ine - pitch b all g rid a rray (tfbga) 8 mm x 10 mm sst p ackage c ode : b1p table 11: r evision h istory number description date 00 initial release jun 2003 01 2004 data book updated b1p package diagram nov 2003 1.2 max h g f e d c b a a b c d e f g h bottom view top view side view 8 7 6 5 4 3 2 1 seating plane 0.35 0.05 0.12 8.00 0.20 0.45 0.05 (56x) 10.00 0.20 0.80 5.60 0.80 5.60 56-tfbga-b1p-8x10-450mic-1 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registere d. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 8 7 6 5 4 3 2 1 1mm a1 corner a1 corner silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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